REG0_TARG=REG0_TARG_0, REG2_ADJ=REG2_ADJ_0, REG1_ADJ=REG1_ADJ_0, REG2_TARG=REG2_TARG_0, REG0_ADJ=REG0_ADJ_0, REG1_TARG=REG1_TARG_0, RAMP_RATE=RAMP_RATE_0
Digital Regulator Core Register
| REG0_TARG | This field defines the target voltage for the ARM core power domain 0 (REG0_TARG_0): Power gated off 1 (REG0_TARG_1): Target core voltage = 0.725V 2 (REG0_TARG_2): Target core voltage = 0.750V 3 (REG0_TARG_3): Target core voltage = 0.775V 16 (REG0_TARG_16): Target core voltage = 1.100V 30 (REG0_TARG_30): Target core voltage = 1.450V 31 (REG0_TARG_31): Power FET switched full on. No regulation. |
| REG0_ADJ | This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0 (REG0_ADJ_0): No adjustment 1 (REG0_ADJ_1): + 0.25% 2 (REG0_ADJ_2): + 0.50% 3 (REG0_ADJ_3): + 0.75% 4 (REG0_ADJ_4): + 1.00% 5 (REG0_ADJ_5): + 1.25% 6 (REG0_ADJ_6): + 1.50% 7 (REG0_ADJ_7): + 1.75% 8 (REG0_ADJ_8): - 0.25% 9 (REG0_ADJ_9): - 0.50% 10 (REG0_ADJ_10): - 0.75% 11 (REG0_ADJ_11): - 1.00% 12 (REG0_ADJ_12): - 1.25% 13 (REG0_ADJ_13): - 1.50% 14 (REG0_ADJ_14): - 1.75% 15 (REG0_ADJ_15): - 2.00% |
| REG1_TARG | This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. 0 (REG1_TARG_0): Power gated off 1 (REG1_TARG_1): Target core voltage = 0.725V 2 (REG1_TARG_2): Target core voltage = 0.750V 3 (REG1_TARG_3): Target core voltage = 0.775V 16 (REG1_TARG_16): Target core voltage = 1.100V 30 (REG1_TARG_30): Target core voltage = 1.450V 31 (REG1_TARG_31): Power FET switched full on. No regulation. |
| REG1_ADJ | This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0 (REG1_ADJ_0): No adjustment 1 (REG1_ADJ_1): + 0.25% 2 (REG1_ADJ_2): + 0.50% 3 (REG1_ADJ_3): + 0.75% 4 (REG1_ADJ_4): + 1.00% 5 (REG1_ADJ_5): + 1.25% 6 (REG1_ADJ_6): + 1.50% 7 (REG1_ADJ_7): + 1.75% 8 (REG1_ADJ_8): - 0.25% 9 (REG1_ADJ_9): - 0.50% 10 (REG1_ADJ_10): - 0.75% 11 (REG1_ADJ_11): - 1.00% 12 (REG1_ADJ_12): - 1.25% 13 (REG1_ADJ_13): - 1.50% 14 (REG1_ADJ_14): - 1.75% 15 (REG1_ADJ_15): - 2.00% |
| REG2_TARG | This field defines the target voltage for the SOC power domain 0 (REG2_TARG_0): Power gated off 1 (REG2_TARG_1): Target core voltage = 0.725V 2 (REG2_TARG_2): Target core voltage = 0.750V 3 (REG2_TARG_3): Target core voltage = 0.775V 16 (REG2_TARG_16): Target core voltage = 1.100V 30 (REG2_TARG_30): Target core voltage = 1.450V 31 (REG2_TARG_31): Power FET switched full on. No regulation. |
| REG2_ADJ | This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. 0 (REG2_ADJ_0): No adjustment 1 (REG2_ADJ_1): + 0.25% 2 (REG2_ADJ_2): + 0.50% 3 (REG2_ADJ_3): + 0.75% 4 (REG2_ADJ_4): + 1.00% 5 (REG2_ADJ_5): + 1.25% 6 (REG2_ADJ_6): + 1.50% 7 (REG2_ADJ_7): + 1.75% 8 (REG2_ADJ_8): - 0.25% 9 (REG2_ADJ_9): - 0.50% 10 (REG2_ADJ_10): - 0.75% 11 (REG2_ADJ_11): - 1.00% 12 (REG2_ADJ_12): - 1.25% 13 (REG2_ADJ_13): - 1.50% 14 (REG2_ADJ_14): - 1.75% 15 (REG2_ADJ_15): - 2.00% |
| RAMP_RATE | Regulator voltage ramp rate. 0 (RAMP_RATE_0): Fast 1 (RAMP_RATE_1): Medium Fast 2 (RAMP_RATE_2): Medium Slow 3 (RAMP_RATE_3): Slow |
| FET_ODRIVE | If set, increases the gate drive on power gating FETs to reduce leakage in the off state |